QG5000XSL9TH Datasheet, PDF (305/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-3.
Snoop Filter Entry
Bits
Value
[23]
State of the cache line
1 The cache line is in E/M state, i.e. the line is either exclusive (but clean) or modified (dirty) state.
0 The cache line is in non-E/M state, i.e. S state if Bus presence vector is non-zero or I state if Bus
presence vector is zero.
[22:21
]
Bus presence vector
[00] The entry is invalid
[xx] The entry is present in any of the processor L2 in the corresponding FSB. Bus0 is the least
significant bit. Bus0 corresponds to FSB0 on the Intel 5000 series chipset MCH. Bus1 corresponding
to FSB1
[20:0] Tag portion of the address
The snoop filter supports the following key operations during normal operation. Due to
timing constraints, these lookup and update commands have been removed for the SF
configuration access.
• SF_Lookup with pLRU status update by MRU operation
On a lookup, the SF uses the tag and set portion of the input address to determine
if the entry is in the SF. The SF asserts a hit if there is a match and provides the
contents, and way information for the matched entry. If the lookup is a miss, the
SF provides the contents of the victim entry, set and way information of the victim.
The pLRU vector is updated according to a Most-Recently-Used (MRU) algorithm.
The SF indicates if a single or double bit error was detected. Single-bit errors are
corrected (but the array is not updated). Hit/miss calculation is performed after the
ECC logic. All FSB request to memory will use this command for SF lookup.
• SF_Lookup with no pLRU status update operation
The SF uses the tag and set portion of the input address to determine if the entry is
in the SF. The SF asserts a hit if there is a match and provides the contents, and
way information for the matched entry. If the lookup is a miss, the SF provides the
contents of the victim entry, set and way information of the victim. The pLRU vector
is not updated. The SF indicates if a single or double bit error was detected. Single-
bit errors are corrected (but the array is not updated). Hit/miss calculation is
performed after the ECC logic. Inbound memory accesses will use this command
for SF lookup.
• SF_Update with pLRU status update by LRU operation
Set and way are provided for write operations. Writes can either be updates or
invalidates. On SF-invalidations, the pLRU array is updated using a Least-Recently-
Used (LRU) entry tracking algorithm. The SF update during inbound write will also
use the “SF_Update with pLRU status update by LRU op” if there is a hit during SF
lookup.
• SF_Update with no pLRU status update operation
Set and way are provided for write operations. The pLRU array is not updated. This
command is used during non-SF-entry-invalidation operations.
5.3
System Memory Controller
The MCH masters four Fully-Buffered DIMM (FB-DIMM) memory channels. Up to four
DIMMs can be connected to each FB-DIMM channel (up to sixteen DIMMs for the entire
array). FB-DIMM memory utilizes a narrow high speed frame oriented interface referred
to as a channel.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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