QG5000XSL9TH Datasheet, PDF (156/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
86h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
86h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
86h
Intel 5000P Chipset
Bit
Attr
Default
Description
5
RO
0h
MRLSS: MRL Sensor State
This bit reports the status of an MRL sensor if it is implemented.
0: MRL Closed
1: MRL Open
4
RWC
0h
CMDCOMP: Command Completed
This bit is set by the Intel 5000P Chipset MCH when the hot-plug controller
completes an issued command and is ready to accept a new command. It is
subsequently cleared by software after the field has been read and processed.
3
RWC
2
RWC
1
RWC
0
RWC
0h
PRSINT: Presence Detect Changed
This bit is set by the Intel 5000P Chipset MCH when a Presence Detect
Changed event is detected. It is subsequently cleared by software after the
field has been read and processed.
0h
MRLSC: MRL Sensor Changed
This bit is set by the Intel 5000P Chipset MCH when an MRL Sensor Changed
event is detected. It is subsequently cleared by software after the field has
been read and processed.
0h
PWRINT: Power Fault Detected
This bit is set by the Intel 5000P Chipset MCH when a power fault event is
detected by the power controller. It is subsequently cleared by software after
the field has been read and processed.
0h
ABP: Attention Button Pressed
This bit is set by the Intel 5000P Chipset MCH when the attention button is
pressed. It is subsequently cleared by software after the field has been read
and processed.
Note that the Assert_intx/Assert_HPGPE message is sent to ESI port when any of the
events defined in bits[4:0] (CMDCOMP,PRSINT, MRLSC, PWRINT, ABP) of the
PEXSLOTSTS register are set provided the corresponding events in bits [4:0] of the
Section 3.8.11.10 and HPINTEN are enabled. Software writes to clear these bits and
MCH will send a Deassert_HPGPE message to ESI port (wired-OR).
For the case when MSI is enabled, any new event that sets these bits (e.g ABP, PRSINT
and so forth) will cause an MSI message to be sent to the FSB for each occurrence.
That is, each bit is considered unique.
Whereas in the case of Legacy interrupts, a wired-OR approach is used to mimic the
level sensitive behavior and only one assert_intx/assert_GPE (deassert_intx/
deassert_GPE) is sent even when multiple interrupt generating bits of the register get
set. Refer to Figure 3-5.
156
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet