QG5000XSL9TH Datasheet, PDF (138/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.11
3.8.11.1
PCI Express Capability Structure
The PCI Express capability structure describes PCI Express related functionality,
identification and other information such as control/status associated with the port. It
is located in the PCI 2.3 compatible space and supports legacy operating system by
enabling PCI software transparent features.
PEXCAPL[7:2, 0]- PCI Express Capability List Register
The PCI Express Capability List register enumerates the PCI Express Capability
structure in the PCI 2.3 configuration space.
3.8.11.2
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
6Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
6Ch
Intel 5000Z Chipset
4-7
0
6Ch
Intel 5000P Chipset
Bit
15:8
Attr
RO
7:0
RO
Default
00h
10h
Description
NXTPTR: Next Ptr
This field is set to NULL pointer to terminate the PCI capability list.
CAPID: Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.
PEXCAP[7:2, 0] - PCI Express Capabilities Register
The PCI Express Capabilities register identifies the PCI Express device type and
associated capabilities.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
6Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
6Eh
Intel 5000Z Chipset
4-7
0
6Eh
Intel 5000P Chipset
Bit
15:14
Attr
RV
Default
0h
Reserved.
Description
138
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet