QG5000XSL9TH Datasheet, PDF (382/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-1. PCI Express Hot-Plug/VPP Block Diagram
FSB 0
FSB 1
Intel ® 5000P chipset
MSI
ICH6/ESB
INTx
PEX Root Port
(P2P bridge, HPC)
VPP
A2 A1 A0
100K Hz SM Bus
I/O extender 0 I/O extender 1
A2 A1 A0
I/O extender 7
Button
LED
Button
LED
Button
LED
Button
LED
Board Power
Manager
Button Button
LED
LED
Slot 0 Slot 1 Slot 2 Slot 3
Slot 14 Slot 15
The Intel 5000X chipset MCH masters a 100KHz hot-plug SMBus interface thru pins
GPIOSMBCLK,and GPIOSMBDATA, for PCI Express ports that connect to a variable
number of serial to parallel I/O ports such as the Phillips PCA9555¹ I/O Extender. The
Intel 5000X chipset MCH only supports SMBus devices with registers mapped as per
Table 5-25. These I/O Extender components have 16 I/Os, divided into two 8-bit ports
that can be configured as inputs or outputs. The Intel 5000X chipset MCH has a
crossbar which associates each PCI Express Hot-Plug Unit (HPU) slots with one of these
8-bit ports. The mapping is defined by a Virtual Pin Port register field, PEXCTRL.VPP, for
each of the PCI Express HPU slots. The VPP register holds the SMBus address and port
number of the IO Port associated with the PCI Express HPU. A[2:0] pins on each I/O
Extender (that is, PCA9555 or compatible components) connected to the Intel 5000X
chipset MCH must strapped uniquely. Table 5-26 defines how the eight hot-plug signals
are mapped to pins on the VPP.
1. Intel 5000X chipset MCH VPP supports PCA9555 or compatible I/O Extender only.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet