QG5000XSL9TH Datasheet, PDF (15/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Table 1-1.
General Terminology (Sheet 3 of 7)
Terminology
Description
Dword
A reference to 32 bits of data on a naturally aligned four-byte boundary (that is, the
least significant two bits of the address are 00b).
ECC
ESB2
Error Correcting Code
Intel^® 631xESB/632xESB I/O Controller Hub
FBD
Fully Buffered DDRII
FBD Channel
One electrical interface to one or more Fully Buffered DDRII DIMM.
FSB
Processor Front-Side Bus. This is the bus that connects the processor to the MCH.
Full Duplex
A connection or channel that allows data or messages to be transmitted in opposite
directions simultaneously.
GART
GB/s
Gb/s
Graphics Aperture Re-map Table. GART is a table in memory containing the page re-
map information used during AGP aperture address translations.
Gigabytes per second (10⁹ bytes per second).
Gigabits per second (10⁹ bits per second).
GTLB
Graphics Translation Look-aside Buffer. A cache used to store frequently used GART
entries.
Hardwired
A parameter that has a fixed value.
Half Duplex
A connection or channel that allows data or messages to be transmitted in either
direction, but not simultaneously.
Host
This term is used synonymously with processor.
I/O
Intel^® 631xESB/
632xESB I/O
Controller Hub
1. Input/Output.
2. When used as a qualifier to a transaction type, specifies that transaction targets
Intel architecture-specific I/O space. (for example, I/O read)
6th Generation I/O Controller Hub. The IO Controller Hub component that contains
the legacy I/O functions.
Implicit Writeback
A snoop initiated data transfer from the bus agent with the modified Cache Line to the
memory controller due to an access to that line.
Inband
Communication that is multiplexed on the standard lines of an interface, rather than
requiring a dedicated signal.
Inbound
See Terminology entry of “Inbound (IB)/Outbound (OB), AKA Upstream/DownStream,
Northbound/Southbound, Upbound/Downbound.”
Incoming
A transaction or data that enters the Intel 5000X chipset.
Inbound (IB)/
Outbound (OB), AKA
Upstream/
DownStream,
Northbound/
Southbound,
Upbound/Downbound
Up, North, or Inbound is in the direction of the processor, Down, South, or Outbound
is in the direction of IO (SDRAM, SMBus).
Initiator
The source of requests. An agent sending a request packet on PCI Express is referred
to as the Initiator for that transaction. The Initiator may receive a completion for the
request.
Isochronous
A classification of transactions or a stream of transactions that require service within a
fixed time interval.
Layer
A level of abstraction commonly used in interface specifications as a tool to group
elements related to a basic function of the interface within a layer and to identify key
interactions between layers.
Legacy
Functional requirements handed down from previous chipsets or PC compatibility
requirements from the past.
Line
Cache line.
Link
The layer of an interface that handles flow control and often error correction by retry.
Lock
A sequence of transactions that must be completed atomically.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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