QG5000XSL9TH Datasheet, PDF (18/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Introduction
Table 1-1.
General Terminology (Sheet 6 of 7)
Terminology
Scalable Bus
SDDC
SDR
SDRAM
SEC/DED
Secondary PCI
Serial Presence
Detect (SPD)
Single-Sided DIMM
Simplex
SMBus
Snooping
Split Lock Sequence
Split Transaction
SSTL
SSTL_2
Symbol
Symbol Time
System Bus
Target
Tenured Transaction
TID
Description
Processor-to-MCH interface. The compatible mode of the Scalable Bus is the P6 Bus.
The enhanced mode of the Scalable Bus is the P6 Bus plus enhancements primarily
consisting of source synchronous transfers for address and data, and FSB interrupt
delivery. The Intel^® Pentium^® 4 processor implements a subset of the enhanced
mode.
Single Device Disable Code; aka x4 or x8 chip-disable Hamming code to protect single
DRAM device (x4 or x8 data width) failure.
Single Data Rate SDRAM.
Synchronous Dynamic Random Access Memory.
Single-bit Error Correct / Double-symbol Error Detect
The physical PCI interface that is a subset of the AGP bus driven directly by the MCH.
It supports a subset of 32-bit, 66 MHz PCI 2.0 compliant components, but only at
1.5 V (not 3.3 V or 5 V).
A two-signal serial bus used to read and write Control registers in the SDRAMs via the
SMBus protocol.
Terminology often used to describe a DIMM that contains one DRAM row. Usually one
row fits on a single side of the DIMM allowing the backside to be empty.
A connection or channel that allows data or messages to be transmitted in one
direction only.
System Management Bus. Mastered by a system management controller to read and
write configuration registers. Signaling and protocol are loosely based on I²C, limited
to 100 KHz.
A means of ensuring cache coherency by monitoring all coherent accesses on a
common multi-drop bus to determine if an access is to information resident within a
cache. The Intel 5000X chipset MCH ensures coherency by initiating snoops on the
processor busses with the address of any line that might appear in a cache on that
bus.
A sequence of transactions that occurs when the target of a lock operation is split
across a processor bus data alignment or Cache Line boundary, resulting in two read
transactions and two write transactions to accomplish a read-modify-write operation.
A transaction that consists of distinct Request and Completion phases or packets that
allow use of bus, or interconnect, by other transactions while the Target is servicing
the Request.
Stub-Series Terminated Logic
Stub Series Terminated Logic for 2.6 Volts (DDR)
An expanded and encoded representation of a data Byte in an encoded system (for
example, the 10-bit value in a 8-bit/10-bit encoding scheme). This is the value that is
transmitted over the physical medium.
The amount of time required to transmit a symbol.
Processor-to-Intel 5000X chipset interface. The system bus in this document refers to
operation at 266/533/1066 MHz (Bus Clock/Address/Data). The system bus is not
compatible with the P6 system bus.
A device that responds to bus Transactions. The agent receiving a request packet is
referred to as the Target for that Transaction.
A transaction that holds the bus, or interconnect, until complete, effectively blocking
all other transactions while the Target is servicing the Request.
Transaction Identifier: A multi-bit field used to uniquely identify a transaction.
Commonly used to relate a Completion with its originating Request in a Split
Transaction system.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet