QG5000XSL9TH Datasheet, PDF (247/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 22
Function: 0
Offset: 298h, 198h
Bit Attr
Default
12:0 RWST
0001h
Description
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
3.9.25.14 FBD[1:0]IBRXSHFT: Intel IBIST Receive Shift Inversion Register
This register indicates which channel is currently inverting the pattern to create cross
talk conditions on the port.
Device: 21
Function: 0
Offset: 298h, 198h
Bit
31:14
Attr
RV
13 RWST
12:0 RWST
Default
0h
0
0001h
Description
Reserved
rxinvshfthi: Receiver Inversion Shift Register for DFT
The pattern loaded in this bit field indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This bit location will experience
rotate-left-shift operation with bits[12:0].
rxinvshft: Receiver Inversion Shift Register
The pattern loaded in this register indicates which lanes are used for
inversion. A logic 1 enables the lane connected to a particular bit position to
invert the pattern that is being transmitted. This register acts as a rotate-left
shift register regardless of the setting of RXINVSWPMD bit. The Modulo-5
value is used to compare each sub-section of the northbound lanes for error
checking.
3.9.25.15 FBD[3:2]LNERR: IBIST Receive Lane Error Register
This register enables IBIST operations for individual lanes.
Device: 22
Function: 0
Offset: 29Ch, 19Ch
Bit
31:14
Attr
RV
13 ROST
12:0 ROST
Default
0h
0
0
Description
Reserved
rxerrstat: Receive error lane status for DFT.
This register records the error from lane 13 of this port.
rxerrstat: Receive error lane status.
This register records the errors from all lanes of this port.
3.9.25.16 FBD[1:0]LNERR: Intel IBIST Receive Lane Error Register
This register enables Intel IBIST operations for individual lanes.
Device: 21
Function: 0
Offset: 29Ch, 19Ch
Bit
31:14
Attr
RV
Default
0h
Reserved
Description
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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