QG5000XSL9TH Datasheet, PDF (227/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.23.3
FBDST[1:0] - FB-DIMM Status
These registers are inspected by software to determine the current FB-DIMM branch
state. This register contains Mirroring recovery state, and Initialization state.
The indexing scheme is the same as in FBDHPC registers. The current FB-DIMM branch
state field indicates state for one or both channels within the same branch depending
on whether the branch is operating in single- or dual-channel mode.
3.9.23.4
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
4Bh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
4Bh
Intel 5000P Chipset
Bit
Attr
Default
Description
7:0 ROST
00h
STATE: FBD Branch State
This field describes the current state of the FB-DIMM branch. It can be read
by software to determine which FB-DIMM branch is being sequenced through
recovery, and how far the FB-DIMM branch has progressed.
00h: Reset
10h: Init
20h: Ready
30h: Active
40h: Redundant
50h: Disabled
60h: Redundancy Loss - may not be written
70h: Recovery Reset - (should only be selected when MC.MIRROR is set)
80h: Recovery Init - (should only be selected when MC.MIRROR is set)
90h: Recovery Ready - (should only be selected when MC.MIRROR is set)
A0h: Reserved
B0h: Recovery Fault
C0h: Recovery Failed
D0h: Fault
This field is only sticky through hard reset when SYRE.S3 is set. This field is
not sticky through hard reset when SYRE.S3 is cleared.
FBDRST[1:0] - FB-DIMM Reset
The FB-DIMM I/O blocks are reset separately from the rest of the Intel 5000P Chipset
MCH. These blocks, composed of FAST-clocked (GHz unit-interval clocked) logic, are
supplied by a PLL whose FBDCLK is not available when PWRGOOD is asserted. After
FBDCLK is enabled and the FB-DIMM PLL has acquired lock, CORERESET# is deasserted
for a minimum of 21ns, then asserted for a minimum of 2us. After the 2us assertion,
CORERESET# is deasserted followed by a minimum delay of 3ns at which time
SOFTCORERESET# is deasserted. If the platform removes FBDCLK on a hot-remove of
the branch, CORERESET# and SOFTCORERESET# must be asserted prior to loss of
FBDCLK.
A “disabled” (not enabled) FBDCLK is floated at the source, and pulled to ground
through the termination near the receiver in the Intel 5000P Chipset MCH.
All timing specifications in Figure 3-6 are minimums. After the sequence in Figure 3-6
has been executed, the FB-DIMM branch is ready for initialization.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
227