QG5000XSL9TH Datasheet, PDF (236/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.24.5
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
B0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
B0h
Intel 5000P Chipset
Bit
Attr Default
15:10 RV
9:5 RWCST
4:0 RWCST
00h Reserved
00h RANK7: Bad device in Rank 7
00h RANK6: Bad device in Rank 6
Description
BADCNT[1:0] - Bad DRAM Counter
This register implements “failing-device” counters for the aliased uncorrectable error
identification algorithm. “Count” double-adjacent symbol errors within x8 devices.
“Drip” each counter after “MC.BADRAMTH” patrol scrub cycles through all of memory.
Values of “MC.BADRAMTH” and “0” cannot be “dripped”. A value of “MC.BADRAMTH”
cannot be incremented. “Mark” the BADRAM(A/B) register when a count reaches
“MC.BADRAMTH”.
3.9.24.6
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
B4h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
B4h
Intel 5000P Chipset
Bit
Attr Default
Description
31:28 RWCST
27:24 RWCST
23:20 RWCST
19:16 RWCST
15:12 RWCST
11:8 RWCST
7:4 RWCST
3:0 RWCST
0000
0000
0000
0000
0000
0000
0000
0000
RANK7: Adjacent x8 symbol error count in Rank 7
RANK6: Adjacent x8 symbol error count in Rank 6
RANK5: Adjacent x8 symbol error count in Rank 5
RANK4: Adjacent x8 symbol error count in Rank 4
RANK3: Adjacent x8 symbol error count in Rank 3
RANK2: Adjacent x8 symbol error count in Rank 2
RANK1: Adjacent x8 symbol error count in Rank 1
RANK0: Adjacent x8 symbol error count in Rank 0
FBDSBTXCFG[1:0][1:0]: FB-DIMM Southbound Transmit Configuration
Register
This register controls the FB-DIMM Southbound I/O Transmit configuration during
normal operation. This value is programmed by BIOS on per channel basis.
236
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet