QG5000XSL9TH Datasheet, PDF (387/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-30. Clock Pins (Sheet 2 of 2)
Pin Name
VSSAPE
VCCACORE
VSSACORE
TCK
GPIOSCL
SCL
OCPSTBP#
OCPSTBN#
PB{0/1}STBP[3:0]#
PB{0/1}STBN[3:0]#
PB{0/1}ADSTB[1:0]#
Pin Description
Analog ground for PCI Express PLLs
Analog power supply for Core PLL
Analog ground for Core PLL
TAP clock
GPIO (Virtual Pin Port) clock
SMBus clock
Debug bus data strobe
Debug bus data strobe (Complement)
Processor bus data strobes
Processor bus data strobes (Complements)
Processor bus address strobes
5.17.6
5.17.6.1
5.17.6.2
5.17.6.3
5.17.6.4
5.17.6.5
High Frequency Clocking Support
Spread Spectrum Support
The Intel 5000X chipset MCH PLLs will support Spread Spectrum Clocking (SSC). SSC
is a frequency modulation technique for EMI reduction. Instead of maintaining a
constant frequency, SSC modulates the clock frequency/period along a predetermined
path, that is, the modulation profile.The Intel 5000X chipset MCH is designed to
support a nominal modulation frequency of 30 KHz with a down spread of 0.5%.
Stop Clock
PLLs in the Intel 5000X chipset MCH cannot be stopped.
Jitter
The FB-DIMM UI clocks are produced by PLLs that multiply the FBDCLK frequency by
12. The PCI Express phit clocks are produced by PLLs that multiply the PECLK
frequency by 25. These multi-GHz phit clocks require ultra-clean sources, ruling out all
but specifically-crafted low-jitter clock synthesizers.
External Reference
An external crystal oscillator is the preferred source for the PLL reference clock. A
spread spectrum frequency synthesizer that meets the jitter input requirements of the
PLL is acceptable.
PLL Lock Time
All PLLs should be locked by PWRGOOD signal assertion. The reference clocks must be
stable 1ms before the assertion of the PWRGOOD signal. The assertion of the
PWRGOOD signal initiates the PLL lock process. External clocks dependent on PLLs are
GPIO clock and SMBus clock. Many JTAG private registers are dependent on core PLL-
generated clocks.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
387