QG5000XSL9TH Datasheet, PDF (321/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Figure 5-10. Code Layout for Dual-Channel Branches
x8 x8 x8 x8 x8 x8 x8 x8 x8
x8 x8 x8 x8 x8 x8 x8 x8 x8
CB
[7:0]
DQ[71:0]
DIMMChannel 1
CB
[7:0]
DQ[71:0]
DIMMChannel 0
Transfer 0
C
S
3
A
C
S
2
A
D
S
3
1
A
D
S
3
0
A
D
S
2
9
A
D
S
2
8
A
D
S
2
7
A
D
S
2
6
A
D
S
2
5
A
D
S
2
4
A
D
S
2
3
A
D
S
2
2
A
D
S
2
1
A
D
S
2
0
A
D
S
1
9
A
D
S
1
8
A
D
S
1
7
A
D
S
1
6
A
C
S
1
A
C
S
0
A
D
S
1
5
A
D
S
1
4
A
D
S
1
3
A
D
S
1
2
A
D
S
1
1
A
D
S
1
0
A
D
S
9
A
D
S
8
A
D
S
7
A
D
S
6
A
D
S
5
A
D
S
4
A
D
S
3
A
D
S
2
A
D
S
1
A
D
S
0
A
Transfer 1
C
S
3
B
C
S
2
B
D
S
3
1
B
D
S
3
0
B
D
S
2
9
B
D
S
2
8
B
D
S
2
7
B
D
S
2
6
B
D
S
2
5
B
D
S
2
4
B
D
S
2
3
B
D
S
2
2
B
D
S
2
1
B
D
S
2
0
B
D
S
1
9
B
D
S
1
8
B
D
S
1
7
B
D
S
1
6
B
C
S
1
B
C
S
0
B
D
S
1
5
B
D
S
1
4
B
D
S
1
3
B
D
S
1
2
B
D
S
1
1
B
D
S
1
0
B
D
S
9
B
D
S
8
B
D
S
7
B
D
S
6
B
D
S
5
B
D
S
4
B
D
S
3
B
D
S
2
B
D
S
1
B
D
S
0
B
Packet
T
R
A
N
S
F
E
R
0
C
D
S
D
D_S
D
D_S
D
D_S
D
D
S
D
D
S
D
C_S
D
D_S
DDDDDDDD
1 _S3 _S2 _S2 _S2 _S1 _S1 _S1 _S1 _SSSSSSSS
2
3
C
S
1
A
D
S
8
A
D
S
5
A
D
S
2
A
D
S
9
A
D
S
6
A
5
C^A
S
D
S
2
A
D
S
9630
ADADADA
SSS
4
5
32
AA
3
0
A
2
9
A
2
7
A
2
6
A
2
4
A
2
3
A
2
1
A
2
0
A
1
8
A
1
7
A
1
0
1
4
AAA
1
3
A
1
1
A
1
0
A
875421
AAAAAA
6
C
D
S
D
D_S
D
D_S
D
D_S
D
D
S
D
D
S
D
C_S
D
D_S
DDDDDDDD
7 _S3 _S2 _S2 _S2 _S1 _S1 _S1 _S1 _SSSSSSSS
8
9
C
S
1
B
D
S
8
B
D
S
5
B
D
S
2
B
D
S
9
B
D
S
6
B
5
C^B
S
D
S
2
B
D
S
9630
BDBDBDB
SSS
1
0
1
1
32
BB
3
0
B
2
9
B
2
7
B
2
6
B
2
4
B
2
3
B
2
1
B
2
0
B
1
8
B
1
7
B
1
0
1
4
BBB
1
3
B
1
1
B
1
0
B
875421
BBBBBB
FFFFFFFFFFFFFFFFFFFFFFFF
DDDDDDDDDDDDDDDDDDDDDDDD
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
1
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
0
N
B
FBD
Signals
y y y y y y y y y y y y y y y y y y y y y y y y y=[P:N]
119876543210119876543210
10
10
Data
Bits
D[0] FD0NBy[0]
DS0
D[1]
[0]
DS0
D[2]
[1]
DS0
D[3]
[2]
DS0
D[128] [3]
DS1
D[129] [0]
DS1
D[130] [1]
DS0
D[131] [4]
DS0
[5]
D[n+2]
DS0
[6]
D[n+3]
DS0
[7]
DS1
[4]
DS1
[5]
D[n]
F
D
D[n+1]
0
N
B
FBD
Signal
y
0
DRAMs
DS0 DS0 DS0 DS0
[3] [2] [1] [0]
D[3] D[2] D[1] D[0]
DS0 DS0 DS0 DS0
[7] [6] [5] [4]
D[131] D[130] D[129] D[128]
DQ[3] DQ[2] DQ[1] DQ[0]
DRAMpins
FBD Branch 0
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
321