QG5000XSL9TH Datasheet, PDF (271/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.11.6
Device: 3-2, 0
Function: 0
Offset: 384h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
384h
Intel 5000Z Chipset
Device: 7-4
Function: 0
Offset: 384h
Version: Intel 5000P Chipset
Bit
31:24
23:16
15:8
7:0
Attr
RW
RW
RW
RW
Default
Description
4Ah
BCh
B5h
BCh
CHARSYM3: Character Symbol [3]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D10.2.
CHARSYM2: Character Symbol [2]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
CHARSYM1: Character Symbol [1]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for D21.5.
CHARSYM0: Character Symbol [0]
This character is symbol [3] of the four-symbol pattern buffer. The default value is
the 8-bit encoding for K28.5.
PEX[7:2,0]IBEXTCTL: PEX Intel IBIST Extended Control
Register
This register extends the functionality of the Intel IBIST with pattern loop counting,
skip character injection, and symbol management. A bit is provided to ignore the count
value and loop continuously for port testing. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
271