QG5000XSL9TH Datasheet, PDF (171/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
130h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
130h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
130h
Intel 5000P Chipset
Bit
Attr
Default
Description
31:27
RO
0h
ADVERR_INT_MSG_NUM: Advanced Error Interrupt Message Number
Advanced Error Interrupt Message Number offset between base message
data an the MSI message if assigned more than one message number to
be used of any status in this capability.
26:7
RV
0h
Reserved
6
RWCST
0
FAT_ERR_Rcvd: Fatal Error Messages Received
Set when one or more Fatal Uncorrectable error Messages¹
have been received.
5
RWCST
0
NFAT_ERR_Rcvd: Non-Fatal Error Messages Received
Set when one or more Non-Fatal Uncorrectable error
Messages have been received.
4
RWCST
0
FRST_UNCOR_FATAL: First Uncorrectable Fatal
Set when the first Uncorrectable error message (which is FATAL) is
received.
3
RWCST
0
MULT_ERR_NOFAT_ERR: Multiple ERR_FATAL NO FATAL_Received
Set when either a fatal or a non-fatal error message is received and
ERR_FAT_NONFAT_RCVD is already set, i.e log from the 2nd Fatal or No
fatal error message onwards
2
RWCST
0
ERR_FAT_NOFAT_RCVD: ERROR FATAL NOFATAL Received
Set when either a fatal or a non-fatal error message is received and this bit
is already not set. That is, log the first error message
1
RWCST
0
MULT_ERR_COR_RCVD: Multiple Correctable Error Received
Set when either a correctable error message is received and
ERR_CORR_RCVD is already set, i.e log from the 2nd Correctable error
message onwards
0
RWCST
0
ERR_CORR_RCVD: First Correctable Error Received
Set when a correctable error message is received and this bit is already not
set. That is, log the first error message
Notes:
1. This applies to both internal generated Root port errors and those messages received from an external source.
3.8.12.17 RPERRSID[7:2, 0] - Error Source Identification Register
The Error Source Identification register identifies the source (Requestor ID) of first
correctable and uncorrectable (Non-fatal/Fatal) errors reported in the Root Error Status
register defined in Section 3.8.12.16. This register is updated regardless of the settings
of the Root Control register defined in Section 3.8.11.12 and the Root Error Command
register defined in.Section 3.8.12.15.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
171