QG5000XSL9TH Datasheet, PDF (307/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Table 5-3.
Maximum 16 DIMM System Memory Configurations
DRAM Technology x8
Single Rank
256 Mb
512 Mb
1024 Mb
2048 Mb
Maximum Capacity
Mirrored Mode
2 GB
4 GB
8 GB
16 GB
Maximum Capacity
Non-Mirrored Mode
4 GB
8 GB
16 GB
32 GB
Note: The Maximum Capacity Mirrored Mode and Maximum Capacity Non-Mirrored Mode columns represent
the system memory available when all DIMM slots are populated with identical x8 Single Rank (x8DR)
DIMMs using the DRAM Technology indicated.
Table 5-4.
Maximum 16 DIMM System Memory Configurations
DRAM Technology x4
Dual Rank
256 Mb
512 Mb
1024 Mb
2048 Mb
Maximum Capacity
Mirrored Mode
8 GB
16 GB
32 GB
32 GB
Maximum Capacity
Non-Mirrored Mode
16 GB
32 GB
64 GB
64 GB
Note: The Maximum Capacity Mirrored Mode and Maximum Capacity Non-Mirrored Mode columns represent
the system memory available when all DIMM slots are populated with identical x4 Double Rank (x4DR)
DIMMs using the DRAM Technology indicated.
5.3.1
Memory Population Rules
DIMM population rules depend on the operating mode of the MC. When operating in
non-mirrored mode the minimum memory upgrade increment is two identical DIMMs
per branch (DIMMs must be identical with respect to size, speed, and organization).
Non-mirrored mode has an exceptional mode that operates with a single DIMM which is
discussed in the following section. When operating in mirrored mode the minimum
upgrade increment is four identical DIMMs
5.3.1.1
Non-Mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must
cover the same slot position on both channels. DIMMs that cover a slot position must
be identical with respect to size, speed, and organization. DIMMs that cover adjacent
slot positions need not be identical.
Within a branch memory DIMMs must be populated in slot order; slot 0 is populated
first, slot 1 second, slot 2 third, and slot 3 last. Slot 0 is closest to the MCH.
Section 5-2 depicts the minimum two DIMM configuration. The populated DIMMs are
depicted in gray (Slot 0 of Branch 0 populated).
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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