QG5000XSL9TH Datasheet, PDF (298/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

System Address Map
4.7.2
Outbound I/O Access
The Intel 5000X chipset allows I/O addresses to be mapped to resources supported on
the I/O buses underneath the MCH. This I/O space is partitioned into 16 4 KB
segments. Each of the I/O buses can have from 1 to 15 segments mapped to it by
programming its IOBASE and IOLIM registers. Each PCI bus must be assigned
contiguous segments. The lowest segment, from 0 to 0-+FFFh, is sent to the ESI.
Figure 4-5. System I/O Address Space
1 0003h
FFFFh
F000h
+3 bytes
(Decoded as
0 000Xh)
Segment F
2000h
Segment 2
through
Segment E
1000h
0000h
Segment 1
Segment 0
Compatability
Bus Only
4.8
Configuration Space
All chipset registers are represented in the memory address map. In addition, some
registers are also mapped as PCI registers in PCI configuration space.These adhere to
the PCI Local Bus Specification, Revision 2.2.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet