QG5000XSL9TH Datasheet, PDF (325/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
5.3.12.3
5.3.12.4
5.3.12.5
CKE State Near End of Activation Throttling Window
If the throttling begins very close to the end of the window, then the assertion of CKE
low command would be delayed beyond the end of the throttle window. To prevent this
occurrence, the memory controller logic does not observe a throttle event in the last
few clocks of the window, or assert a CKE low command.
If the activation throttle is set to begin within Y clocks before the end of the window,
the memory controller skips the asserting CKE low step, where Y is X + 6¹ (and the
number “6” is derived from 3 clocks for the CKE low to high minimum, plus another 3
clocks for the CKE high until first command after the throttling window.
Refresh Handling During Throttling
The Intel 5000X chipset memory controller ensures that refreshes, which are lost
during the activation throttle period (possibly up to 2), are made up at the end of the
period. Double refresh rates to the DIMMs should be carried out when needed
regardless of the setting of the MC.THRMHUNT bit. This is particularly important for
open loop throttling when the temperature could rise beyond 85’C.
Throttling Parameters for Activation Throttling.
The current throttling parameters for each branch are stored in the THRMTHRT register
field defined in Section 3.9.3. All activation throttling parameters in the THRMTHRT
registers are 8-bits wide, and provide increments of 4 activations per throttle window
(1344 clocks). Three levels of throttling limits are defined.
• THRTLOW: A base throttling level that is applied when the temperature is in the low
range (below T_low) and the THRTSTS.GBLTHRT*² bit is not set by the Global
Throttling Window logic. See Section 3.9.4
• THRTMID: A mid level throttling level that is applied when the temperature is in the
middle range (above T_low but below T_mid) or the THRSTS.GBLTHRT* bit is set by the
Global Throttling Window logic. See Section 3.9.5
• THRTHI: The highest level of throttling. When MC.THRMODE=1, this level is applied
whenever the temperature is above T_mid. When MC.THRMODE=0, this level is the
ceiling of the hunting algorithm of the closed loop throttling. The temperature being
above T_mid has priority over the Global Throttling Window throttling (the higher
throttling level takes precedence). See Section 3.9.6
The MC.THRMHUNT bit must be enabled for the temperature to have any influence on
the throttle parameters. If MC.THRMHUNT=0, only the GBLTHRT bit from the Global
Throttle Window, when enabled can change the THRMTHRT register field. Refer to
Figure 5-11 and Figure 5-12 for the thermal envelopes.
1. Intel 5000X chipset MC design needs to adjust the value based on the latest JEDEC
recommendation for CKE low to high transition.
2. GBLTHRT* is an internal combinatorial signal before it is latched in the THRSTS.GBLTHRT register
field to enable the open loop throttling logic to use the latest value of the signal.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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