QG5000XSL9TH Datasheet, PDF (269/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.11.4
PEX[7:2,0]IBCTL: PEX Intel IBIST Control Register
This register contains the control bits and status information necessary to operate the
Fixed and Open modes of the Intel IBIST logic. The default settings allow the CMM logic
to operate with link width of a PEX port. Only valid PCI Express control characters/
symbols are allowed for Intel IBIST testing.
Device: 3-2, 0
Function: 0
Offset: 380h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
380h
Intel 5000Z Chipset
Device: 7-4
Function: 0
Offset: 380h
Version: Intel 5000P Chipset
Bit
31
30
29
28
27:23
22:14
13:9
8
Attr
RW
RW
RW
RW
RV
RO
RO
RWCST
Default
Description
SYMTYPSEL3: Symbol[3] Type Select
0
1: selects Symbol [3] as a control character
0: selects Symbol [3] to a data character
SYMTYPSEL2: Symbol[2] Type Select
1
1: selects Symbol [2] as a control character
0: selects Symbol [2] to a data character
SYMTYPSEL1: Symbol[1] Type Select
0
1: selects Symbol [1] as a control character
0: selects Symbol [1] to a data character
SYMTYPSEL0: Symbol[0] Type Select
1
1: selects Symbol [0] as a control character
0: selects Symbol [0] to a data character
0
Reserved
ERRVAL: Error Value
This is the raw 9-bit error value captured on the lane that asserted the Error
0h _{Detected bit (ERRDET) or the Global Error status bit if this register is}
implemented. The value must be extracted in the datapath before the 10b/8b
decoder in order to examine its contents for debugging potential link errors.
ERRLNNUM: Error Lane Number
This field indicates which lane reported the error that was detected when
ERRDET was asserted.
0h _{Note: When the number of lanes reporting exceeds 32, this field will show an}
aliased error lane number and cannot be used to indicate the errant lane.
Larger lane indications will require an extended register to display accurate
information.
ERRDET: Error Detected
A mis-compare between the transmitted symbol and the symbol received on
link indicates an error condition occurred. Refer to Error Value, Error Symbol
Pointer and Error Symbol Type bit fields for further information about fault
locations. This bit is cleared by writing a logic ‘1’ and it remains asserted
through reset (sticky).
0
0: No error detected
1: Error Detected
Note: The error signal that causes this bit to be set should be made available
externally to the Intel IBIST logic. It is implementation specific as to how this
is accomplished. The purpose is for symbol (bit) error rate testing. It is
assumed that this signal is either sent to a performance counter or an
external pin for signal assertion accumulation. There is not any error counting
resources available in this spec.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
269