QG5000XSL9TH Datasheet, PDF (267/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
8
0
76h
Intel 5000P Chipset
Bit
1
0
Attr Default
Description
RWC 0
RWC 0
NFED: Non-Fatal Error Detected
This bit gets set if a non-fatal uncorrectable error is detected.
Errors are logged in this register regardless of whether error reporting is enabled or
not in the Device Control register. (See NFERE in Section 3.10.18)
1: Non Fatal errors detected
0: No non-Fatal Errors detected
CED: Correctable Error Detected
This bit gets set if a correctable error is detected. Errors are logged in this register
regardless of whether error reporting is enabled or not in the Device Control
register. (See CERE in Section 3.10.18)
1: correctable errors detected
0: No correctable errors detected
3.11
3.11.1
PCI Express Intel IBIST Registers
DIOIBSTR: PCI Express Intel IBIST Global Start/Status
Register
This register contains the global start for all the ports in the Intel 5000P Chipset MCH
component simultaneously. One start bit is placed in the register for each port. Intel
IBIST will start at approximately the same time on all ports written to with a 1 in the
same write access.
Device:
Function:
Offset:
Version:
0
0
398h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit Attr Default
Description
7
RW
6
RW
5
RW
4
RW
3
RW
2
RW
1
RV
0
RW
0
START7: Writing a 1 starts Intel IBIST on port 7.
0
START6: Writing a 1 starts Intel IBIST on port 6.
0
START5: Writing a 1 starts Intel IBIST on port 5.
0
START4: Writing a 1 starts Intel IBIST on port 4.
0
START3: Writing a 1 starts Intel IBIST on port 3.
0
START2: Writing a 1 starts Intel IBIST on port 2.
0
Reserved
0
START0: Writing a 1 starts Intel IBIST on port 0.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
267