QG5000XSL9TH Datasheet, PDF (201/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
16
1
160h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
Default
Description
RWST
11111111h
FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to Table 3-38 for the programming details.
Table 3-38. FB-DIMM to Host Gear Ratio Mux
FSB:Memory Frequency
Gear Ratio¹
Value
333:333
267:267
400:400
1:1
11111111h
333:267
5:4
00023230h
267:333
4:5 (conservative)
00004323h
267:333
4:5 (aggressive)
00002323h
Notes:
1. For 4:5 gear ratio, software should use either conservative or aggressive mode for all the
respective memory gearing registers (no mix and match).
3.9.11 FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio
Configuration 1
This register consists of eight nibbles of mux select data for the proper selection of
gearing behavior on the FB-DIMM for the 1:1 and 4:5 modes.This is the second register
for FB-DIMM to Host gearing control.
Device:
Function:
Offset:
Version:
16
1
164h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31:0
Attr
Default
Description
RWST
00000000h
FBDHSTGRMUX: FB-DIMM to Host Clock Gearing mux selector.
Eight nibbles of mux select for memory/DDR2 to FSB/core geared clock
boundary crossing phase enables.
Refer to Table 3-39 for the programming details.
Table 3-39. FB-DIMM to Host Gear Ratio Mux
FSB:Memory Frequency
Gear Ratio¹
333:333
267:267
400:400
333:267
267:333
267:333
1:1
5:4
4:5 (conservative)
4:5 (aggressive)
Value
00000000h
00000000h²
00002000h
00000400h
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
201