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| QG5000XSL9TH Datasheet, PDF (35/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH) | |||
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Signal Description
⢠BUSCLK must be valid at least 2ms prior to rising edge of PWRGOOD.
Figure 2-1. Intel 5000X Chipset Clock and Reset Requirements
Power Rails
PWRGOOD
RESET#
BUSCLK
~100ms
2ms
1ms
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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