QG5000XSL9TH Datasheet, PDF (397/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Testability
Figure 6-2. TAP Controller State Machine
The following list describes the behavior of each state in the TAP.
Test-Logic-Reset: In this state, the test logic is disabled so that normal operation of
the device can continue unhindered. The instruction in the Instruction Register is forced
to IDCODE. The controller is guaranteed to enter Test- Logic-Reset when the TMS input
is held active for at least five clocks. The controller also enters this state immediately
when TRST# is pulled active. The TAP controller cannot leave this state as long as
TRST# is held active.
Run-Test/Idle: The TAP idle state. All test registers retain their previous values.
Capture-IR: In this state, the shift register contained in the Instruction Register loads
a fixed value (of which the two least significant bits are “01”) on the rising edge of TCK.
The parallel, latched output of the Instruction Register (“current instruction”) does not
change.
Shift-IR: The shift register contained in the Instruction Register is connected between
TDI and TDO and is shifted one stage toward its serial output on each rising edge of
TCK. The output arrives at TDO on the falling edge of TCK. The current instruction does
not change.
Pause-IR: Allows shifting of the Instruction Register to be temporarily halted. The
current instruction does not change.
Update-IR: The instruction which has been shifted into the Instruction Register is
latched onto the parallel output of the Instruction Register on the falling edge of TCK.
Once the new instruction has been latched, it remains the current instruction until the
next Update-IR (or until the TAP controller state machine is reset).
Capture-DR: In this state, the Data Register selected by the current instruction may
capture data at its parallel inputs.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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