QG5000XSL9TH Datasheet, PDF (115/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Memory range covered by MBASE and MLIM registers, are used to map non-
prefetchable PCI Express address ranges (typically where control/status memory-
mapped I/O data structures reside) and PMBASE and PMLIM are used to map
prefetchable address ranges. This segregation allows application of USWC space
attribute to be performed in a true plug-and-play manner to the prefetchable address
range for improved PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers such as MIR, MLIM, MBASE, IOLIM, IOBASE, PMBASE, PMLIM, PMBU, PMLU
(coherent, MMIO, prefetchable, non-prefetchable, I/O) with the values that provide
exclusive address ranges, that is, prevent overlap with each other and/or with the
ranges covered with the main memory. There is no provision in the MCH hardware to
enforce prevention of overlap and operations of the system in the case of overlap are
not guaranteed.
3.8.8.18
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
22h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
22h
Intel 5000Z Chipset
4-7
0
22h
Intel 5000P Chipset
Bit
15:4
Attr
RW
3:0
RO
Default
0h
0h
Description
MLIMIT: Memory Limit Address
Corresponds to A[31:20] of the memory address that corresponds to the upper
limit of the range of memory accesses that will be passed by the PCI Express
bridge
Reserved. (by PCI SIG)
PMBASE[7:2] - Prefetchable Memory Base
The Prefetchable Memory Base and Memory Limit registers define a memory mapped
I/O prefetchable address range (32-bit addresses) which is used by the PCI Express
bridge to determine when to forward memory transactions based on the
following formula:
PREFETCH_MEMORY_BASE <= A[31:20] <= PREFETCH_MEMORY_LIMIT
The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers
are read/write and corresponds to the upper 12 address bits, A[31:20], of 32-bit
addresses. For the purpose of address decoding, the bridge assumes that the lower 20
address bits, A[19:0], of the memory base address are zero. Similarly, the bridge
assumes that the lower 20 address bits, A[19:0], of the memory limit address (not
implemented in the Memory Limit register) are F FFFFh. Thus, the bottom of the
defined memory address range will be aligned to a 1 MB boundary and the top of the
defined memory address range will be one less than a 1 MB boundary.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
115