QG5000XSL9TH Datasheet, PDF (24/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Signal Description
2.6 VGPIO 2.6 V buffers used for miscellaneous GPIO signals
CMOS CMOS buffers
Host Interface signals that perform multiple transfers per clock cycle may be marked as
either “4X” (for signals that are “quad-pumped”) or 2X (for signals that are “double-
pumped”).
Note:
Processor address and data bus signals are logically inverted signals. In other words,
the actual values are inverted of what appears on the processor bus. This must be
taken into account and the addresses and data bus signals must be inverted inside the
MCH host bridge. All processor control signals follow normal convention. A 0 indicates
an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an
active level (high voltage) if the signal has no # suffix.
Table 2-1. Signal Naming Conventions
Convention
Expands to
RR{0/1/2}XX
Expands to: RR0XX, RR1XX, and RR2XX. This denotes similar signals
on replicated buses.
RR[2:0]
Expands to: RR[2], RR[1], and RR[0]. This denotes a bus.
RR{0/1/2}
Expands to: RR2, RR1, and RR0. This denotes electrical duplicates.
RR# or RR[2:0]# Denotes an active low signal or bus.
Table 2-2 lists the reference terminology used for signal types.
Table 2-2.
Buffer Signal Types
Buffer
Direction
I
O
A
I/O
Description
Input signal
Output signal
Analog
Bidirectional (input/output) signal
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet