QG5000XSL9TH Datasheet, PDF (351/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Functional Description
Each of the Intel 5000X chipset MCH PCI Express port are organized as four bi-
directional bit lanes, and are referred to as a x4 port.
5.13.2
Enterprise South Bridge Interface (ESI)
The ESI is the Intel 631xESB/632xESB I/O Controller Hub to Intel 5000X chipset MCH
interface. The available bandwidth to the Intel 631xESB/632xESB I/O Controller Hub
can be increased by using the one or more of the PCI Express ports 2 and 3.
Figure 5-18 depicts the ESI port and PCI Express ports 2 and 3.
5.13.3 PCI Express Ports 2 and 3
The PCI Express ports 2 and 3 are general purpose x4 PCI Express ports that may be
used to connect to PCI Express devices. The possible configurations of the PCI Express
ports are depicted in Figure 5-18. By configuring ports 2 and 3 with the ESI port to the
Intel 631xESB/632xESB I/O Controller Hub, bandwidth is definable from 1GB/s in each
direction up to a maximum of 6 GB/s bi-directional. Figure 5-19 depicts the various
combinations of ESI and ports 2 and 3 connecting to the Intel 631xESB/632xESB I/O
Controller Hub. Ports 2 and 3 are also general purpose PCI Express ports that may be
used as high performance interfaces to other PCI Express devices.
Figure 5-18. ESI and PCI Express Ports 2 and 3
M CH
T ra n s a c tio n
L in k
P h y s ic a l
P o rt 0
DM I
P h y s ic a l
L in k
T ra n s a c tio n
I n te l® 6 3 1 x E S B / 6 3 2 x E S B I / O
C o n tr o lle r H u b
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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