QG5000XSL9TH Datasheet, PDF (86/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.2.7
Device:
Function:
Offset:
Version:
16
0
5Eh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
1:0
RW
00
LOENABLE5: 0E0000-0E3FFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E0000-0E3FFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
PAM6 - Programmable Attribute Map Register 6
This register controls the read, write, and shadowing attributes of the BIOS areas which
extend from 0E 8000h -0E FFFFh.
Device:
Function:
Offset:
Version:
16
0
5Fh
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7:6
RV
5:4
RW
3:2
RV
1:0
RW
00
Reserved
00
ESIENABLE6: 0EC000-0DFFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0EC000-0DFFFF.
Bit5 = Write enable, Bit4 = Read enable.
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
00
Reserved
00
LOENABLE6: 0E8000-0EBFFF Attribute Register
This field controls the steering of read and write cycles that address the BIOS
area from 0E8000-0EBFFF.
Bit1 = Write enable, Bit0 = Read enable
Encoding Description
00: DRAM Disabled - All accesses are directed to ESI
01: Read Only - All reads are serviced by DRAM. Writes are forwarded to ESI
10: Write Only - All writes are sent to DRAM. Reads are serviced by ESI
11: Normal DRAM Operation - All reads and writes are serviced by DRAM
86
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet