QG5000XSL9TH Datasheet, PDF (4/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

3.9
3.10
3.8.4 Interrupt Redirection Registers .................................................................93
3.8.5 Boot and Reset Registers .........................................................................94
3.8.6 Control and Interrupt Registers ................................................................98
3.8.7 PCI Express Device Configuration Registers .............................................. 100
3.8.8 PCI Express Header .............................................................................. 102
3.8.9 PCI Express Power Management Capability Structure................................. 131
3.8.10 PCI Express Message Signaled Interrupts (MSI) Capability Structure............ 134
3.8.11 PCI Express Capability Structure ............................................................. 138
3.8.12 PCI Express Advanced Error Reporting Capability ...................................... 160
3.8.13 Error Registers ..................................................................................... 182
Memory Control Registers ................................................................................. 194
3.9.1 MC - Memory Control Settings ................................................................ 194
3.9.2 GBLACT - Global Activation Throttle Register ............................................ 196
3.9.3 THRTSTS[1:0] - Thermal Throttling Status Register................................... 197
3.9.4 THRTLOW - Thermal Throttling Low Register ............................................ 198
3.9.5 THRTMID - Thermal Throttle Mid Register ................................................ 198
3.9.6 THRTHI - Thermal Throttle High Register ................................................. 199
3.9.7 THRTCTRL - Thermal Throttling Control Register ....................................... 199
3.9.8 MCA - Memory Control Settings A ........................................................... 199
3.9.9 DDRFRQ - DDR Frequency Ratio ............................................................. 200
3.9.10 FBDTOHOSTGRCFG0: FB-DIMM to Host Gear Ratio Configuration 0.............. 200
3.9.11 FBDTOHOSTGRCFG1: FB-DIMM to Host Gear Ratio Configuration 1.............. 201
3.9.12 HOSTTOFBDGRCFG: Host to FB-DIMM Gear Ratio Configuration .................. 202
3.9.13 GRFBDVLDCFG: FB-DIMM Valid Configuration ........................................... 202
3.9.14 GRHOSTFULLCFG: Host Full Flow Control Configuration.............................. 204
3.9.15 GRBUBBLECFG: FB-DIMM Host Bubble Configuration ................................. 204
3.9.16 GRFBDTOHOSTDBLCFG: FB-DIMM To Host Double Configuration ................. 205
3.9.17 Summary of Memory Gearing Register operating modes ............................ 205
3.9.18 DRTA - DRAM Timing Register A ............................................................. 205
3.9.19 DRTB - DDR Timing Register B ............................................................... 207
3.9.20 ERRPER - Error Period ........................................................................... 208
3.9.21 Memory Map Registers .......................................................................... 208
3.9.22 FB-DIMM Error Registers........................................................................ 210
3.9.23 FB-DIMM Branch Registers ..................................................................... 225
3.9.24 FB-DIMM RAS Registers......................................................................... 234
3.9.25 FB-DIMM Intel IBIST Registers ............................................................... 237
3.9.26 Serial Presence Detect Registers ............................................................. 252
DMA Engine Configuration Registers ................................................................... 253
3.10.1 PCICMD: PCI Command Register ............................................................ 253
3.10.2 PCISTS: PCI Status Register .................................................................. 255
3.10.3 CCR: Class Code Register ...................................................................... 256
3.10.4 CB_BAR: DMA Engine Base Address Register ............................................ 256
3.10.5 CAPPTR: Capability Pointer Register ........................................................ 257
3.10.6 INTL: Interrupt Line Register.................................................................. 257
3.10.7 INTP: Interrupt Pin Register ................................................................... 257
3.10.8 Power Management Capability Structure .................................................. 257
3.10.9 MSICAPID - Message Signalled Interrupt Capability ID Register................... 260
3.10.10MSINXPTR - Message Signalled Interrupt Next Pointer Register ................... 260
3.10.11MSICTRL - Message Signalled Interrupt Control Register ............................ 260
3.10.12MSIAR: Message Signalled Interrupt Address Register ............................... 262
3.10.13MSIDR: Message Signalled Interrupt Data Register.................................... 262
3.10.14PEXCAPID: PCI Express Capability ID Register .......................................... 263
3.10.15PEXNPTR: PCI Express Next Pointer Register ............................................ 263
3.10.16PEXCAPS - PCI Express Capabilities Register ............................................ 264
3.10.17PEXDEVCAP - Device Capabilities Register ................................................ 264
3.10.18PEXDEVCTRL - Device Control Register .................................................... 265
4
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet