QG5000XSL9TH Datasheet, PDF (251/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 21
Function: 0
Offset: 2A8h, 1A8h
Bit
31:14
Attr
RV
Default
0h
13:10 RWST
Fh
9:0 RWST
3FFh
Description
Reserved
txpatt2hvmen: receiver Pattern Buffer 2 Enable for the HVM lanes
Selects which channels to enable the second pattern buffer.
txpatt2en: receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
3.9.25.23 FBD[3:2]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device: 22
Function: 0
Offset: 2ACh, 1ACh
Bit
31:14
Attr
RV
Default
0h
13:0 RWST
3FFFh
Description
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
3.9.25.24 FBD[1:0]IBRXPAT2EN: Intel IBIST RX Pattern Buffer 2 Enable
This register enables inversion pattern testing on individual lanes.
Device: 21
Function: 0
Offset: 2ACh, 1ACh
Bit
31:14
Attr
RV
Default
0h
13:0 RWST
3FFFh
Description
Reserved
rxpatt2en: Receiver Pattern Buffer 2 Enable
Selects which channels to enable the second pattern buffer.
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
251