QG5000XSL9TH Datasheet, PDF (116/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.8.19
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
24h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
24h
Intel 5000Z Chipset
4-7
0
24h
Intel 5000P Chipset
Bit
15:4
Attr
RW
3:0
RO
Default
0h
1h
Description
PMBASE: Prefetchable Memory Base Address
Corresponds to A[31:20] of the prefetchable memory address on the PCI
Express port.
PMBASE_CAP: Prefetchable Memory Base Address Capability
0h – 32 bit Prefetchable Memory addressing
1h – 64bit Prefetchable Memory addressing,
others - Reserved.
The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory
Limit registers are read-only, contain the same value, and encode whether or not the
bridge supports 64-bit addresses. If these four bits have the value 0h, then the bridge
supports only 32 bit addresses. If these four bits have the value 01h, then the bridge
supports 64-bit addresses and the Prefetchable Base Upper 32 bits and Prefetchable
Limit Upper 32 bits registers hold the rest of the 64-bit prefetchable base and limit
addresses respectively.
PMLIM[7:2] - Prefetchable Memory Limit
This register controls the processor to PCI Express prefetchable memory access routing
based on the following formula as described above:
PREFETCH_MEMORY_BASE <= A[31:20] <= PREFTCH_MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. This register must be initialized by the
configuration software. For the purpose of address decode address bits A[19:0] are
assumed to be F FFFFh.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
2-3
0
26h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-7
0
26h
Intel 5000P Chipset
Bit
15:4
Attr
RW
Default
0h
Description
PMLIMIT: Prefetchable Memory Limit Address
Corresponds to A[31:20] of the memory address on the PCI Express bridge
116
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet