QG5000XSL9TH Datasheet, PDF (194/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.8.13.28 MCERR_INT - Internal MCERR Mask Register
This register enables the signaling of MCERR when an error flag is set. Note that one
and only one error signal should be enabled. Note that one and only one error signal
should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and MCERR_INT for each of
the corresponding bits.
3.9
3.9.1
Device:
Function:
Offset:
Version:
16
2
D3h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RWST
6
RWST
5
RWST
4
RWST
3
RWST
2
RWST
1
RWST
0
RWST
1
B8McErrMsk: SF Coherency Error for BIL
1
B7McErrMsk: Multiple ECC error in any of the ways during SF lookup
1
B6McErrMsk: Single ECC error on SF lookup
1
B5McErrMsk: Address Map Error
1
B4McErrMsk: SMBus Virtual Pin Error
1
B3McErrMsk: Coherency Violation Error for EWB
1
B2McErrMsk: Multi-Tag Hit SF
1
B1McErrMsk: DM Parity Error
Memory Control Registers
MC - Memory Control Settings
Miscellaneous controls not implemented in other registers.
Device:
Function:
Offset:
Version:
16
1
40h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
31
30
29
28:25
24:22
21
Attr
RV
RW
RV
RW
RV
RW
Default
Description
0
Reserved
0
RETRY: Retry Enable
‘1’ = enables retry.
‘0’ = disables retry.
0
Reserved
0h BADRAMTH: BADRAM Threshold
Number of consecutive instances of adjacent symbol errors required to mark a bad
device in a rank. Number of patrol scrub cycles required to decrement a non-
saturated BADCNT.
If Software desires to enable the “enhanced mode” and use the BADRAMTH, it
needs to set a non-zero value to this register field prior. Otherwise, a value of 0 is
considered illegal and memory RAS operations may lead to indeterministic
behavior.
0
Reserved
0
INITDONE: Initialization Complete. This scratch bit communicates software
state from Intel 5000P Chipset MCH to BIOS. BIOS sets this bit to 1 after
initialization of the DRAM memory array is complete. This bit has no effect on Intel
5000P Chipset MCH operation.
194
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet