QG5000XSL9TH Datasheet, PDF (230/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
3.9.23.7
MTR[1:0][3:0] - Memory Technology Registers
These registers define the organization of the DIMM’s. There is one MTR for each pair of
slots comprising either one or two ranks. The parameters for these devices can be
obtained by serial presence detect.
MTR[3:0] defines slot-pairs [3:0] on branch[0]. MTR[7:4] defines slot-pairs [3:0] on
branch[1].
MTR[3:0] in Table 3-24 is MTR[3:0] for Device 21 which is MTR[3:0] for this
Section 3.9.23.7.
MTR[3:0] in Table 3-24 is MTR[3:0] for Device 22 which is MTR[7:4] for this
Section 3.9.23.7.
This register must not be modified while servicing memory requests.
3.9.23.8
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
21
0
8Ch, 88h, 84h, 80h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
22
0
8Ch, 88h, 84h, 80h
Intel 5000P Chipset
Bit
15:9
8
7
6
5
4
3:2
1:0
Attr Default
Description
RV
00h Reserved
RW
0
PRESENT: DIMMs are present
This bit is set if both DIMMs are present and their technologies are compatible.
RW
0
ETHROTTLE: Technology - Electrical Throttle
Defines the electrical throttling level for these DIMMs:
‘0’ = Electrical Throttling is disabled
‘1’ = Electrical Throttling is enabled using the throttling level defined by the
MC.ETHROT configuration field.
RW
0
WIDTH: Technology - Width
Defines the data width of the SDRAMs used on these DIMMs
‘0’ = x4 (4 bits wide)
‘1’ = x8 (8 bits wide)
RW
0
NUMBANK: Technology - Number of Banks
Defines the number of (real, not shadow) banks on these DIMMs
‘0’ = four-banked
‘1’ = eight-banked
RW
0
NUMRANK: Technology - Number of Ranks
Defines the number of ranks on these DIMMs.
‘0’ = single ranked
‘1’ = double ranked
RW
00 NUMROW: Technology - Number of Rows
Defines the number of rows within these DIMMs.
“00”= 8,192, 13 rows
“01”= 16,384, 14 rows
“10”= 32,768, 15 rows
“11”= Reserved
RW
00 NUMCOL: Technology - Number of Columns
Defines the number of columns within these DIMMs
“00”= 1,024, 10 columns
“01”= 2,048, 11 columns
“10”= 4,096, 12 columns
“11”= Reserved
DMIR[1:0][4:0] - DIMM Interleave Range
These registers define rank participation in various DIMM interleaves.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet