QG5000XSL9TH Datasheet, PDF (168/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
118h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
118h
Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-7
0
118h
Intel 5000P Chipset
Bit
31:9
8
Attr
RV
RO
7
RO
6
RO
5
RO
4:0 ROST
Default
0h
0
0
0
0
0h
Description
Reserved
ECRCCHKEN: ECRC Check Enable
This bit when set enables ECRC checking.
ECRCCHKCAP: ECRC Check Capable
Intel 5000P Chipset MCH does not support ECRC.
ECRCGENEN: ECRC Generation Enable
Intel 5000P Chipset MCH does not generate ECRC.
ECRCGENCAP: ECRC Generation Capable
Intel 5000P Chipset MCH does not generate ECRC.
FERRPTR: First error pointer
The First Error Pointer is a read-only register that identifies the bit position
of the first error reported in the Uncorrectable Error status register. Left
most error bit if multiple bits occurred simultaneously.
3.8.12.11 HDRLOG0[7:2, 0] - Header Log 0
This register contains the first 32 bits of the header log locked down when the first
uncorrectable error occurs. Headers of the subsequent errors are not logged.
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
Device:
Function:
Offset:
Version:
0, 2-3
0
11Ch
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
4-5
0
11Ch
Intel 5000Z Chipset
4-7
0
11Ch
Intel 5000P Chipset
Bit
31:0
Attr
ROST
Default
0h
Description
HDRLOGDW0: Header of TLP (DWORD 0) associated with first
uncorrectable error
3.8.12.12 HDRLOG1[7:2, 0] - Header Log 1
This register contains the second 32 bits of the header log.
168
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet