QG5000XSL9TH Datasheet, PDF (193/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device:
Function:
Offset:
Version:
16
2
D1h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
4
RWST
1
B5Err1Msk: Address Map Error
3
RWST
2
RWST
1
RWST
0
RWST
1
B4Err1Msk: SMBus Virtual Pin Error
1
B3Err1Msk: Coherency Violation Error
1
B2Err1Msk: Multi-Tag Hit SF
1
B1Err1Msk: DM Parity Error
3.8.13.27 ERR0_INT - Internal Error 0 Mask Register
This register enables the signaling of Err[0] when an error flag is set. Note that one and
only one error signal should be enabled in the ERR2_INT, ERR1_INT, ERR0_INT, and
MCERR_INT for each of the corresponding bits.
Device:
Function:
Offset:
Version:
16
2
D0h
Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Bit
Attr
Default
Description
7
RWST
6
RWST
5
RWST
4
RWST
3
RWST
2
RWST
1
RWST
0
RWST
1
B8Err0Msk: SF Coherency Error for BIL
1
B7Err0Msk: Multiple ECC error in any of the ways during SF lookup
1
B6Err0Msk: Single ECC error on SF lookup
1
B5Err0Msk: Address Map Error
1
B4Err0Msk: SMBus Virtual Pin Error
1
B3Err0Msk: Coherency Violation Error for EWB
1
B2Err0Msk: Multi-Tag Hit SF
1
B1Err0Msk: DM Parity Error
Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet
193