QG5000XSL9TH Datasheet, PDF (272/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

Register Description
Device: 3-2, 0
Function: 0
Offset: 388h
Version: Intel 5000P Chipset, Intel 5000V Chipset, Intel 5000Z Chipset
Device:
Function:
Offset:
Version:
4-5
0
388h
Intel 5000Z Chipset
Device: 7-4
Function: 0
Offset: 388h
Version: Intel 5000P Chipset
Bit
31:29
28
27:26
25
24
23:12
11:0
Attr
RV
RW
RW
RW
RW
RW
RW
Default
Description
0h
0
01
0
0
000h
07Fh
Reserved
FRCENT: Forced Entry:
Setting this bit forces entry into master Intel IBIST loopback state when the Start
bit is asserted. No TS1s are sent when enabled. The Intel IBIST is granted direct
control of the transmitted path regardless of which state the LTSSM is in. The Intel
IBIST state machine sends the contents of the pattern buffer until the stop
condition is reached. The receiver isn’t expected to perform any error checking
and must ignore input symbols.
NOTE: For Intel 5000P Chipset MCH the user must reset the component to stop
this function. The
receiver sets the done condition and the receiver is disabled with this function.
0: Execute normally
1: Force to Loopback state as a ‘master’ condition.
LNMODUEN: Lane Modulo Enable for Delay Symbol Injection
00: No symbols sent on lanes
01: Delay symbols sent on modulo 4 group of lanes across the width of the port.
10: Delay symbols sent on modulo 8 group of lanes across the width of the port.
11: Reserved
DISSTOP: Disable Stop on Error
0: Enable Stop on Error
1: Disable Stop on Error. The Intel IBIST engine continues to run in its current
mode in the presence of an error. If an error occurs overwrite the error status
collected from a previous error event.
LPCON: Loop Continuously
0: Use loop counter. Test terminates at the end of the global count.
1: Loop symbols continuously.
SKPCNTINT: Skip Count Interval
This register indicates when a skip order sequence is sent on the transmitter. Upon
reaching this count the transmitter sends an SOS then clears the skip counter and
counting resumes until the next match on the skip count interval.
000: No Skip Ordered Sets are sent on TX.
nnn: The number of 8 symbol sets transmitted before a Skip Ordered Set is sent.
LOOPCNTLIM: Loop Count Limit
This register indicates the number of times the data symbol buffer is looped as a
set of 8 symbol times. If LOOPCON is set then this count limit is ignored.
00: No symbols are sent from symbol buffer unless LOOPCON is set. If LOOPCON
is cleared and this value is 000h then the transmitter immediately exits out of
loopback state by sending EIOS without sending a pattern buffer payload.
01-FFF: 1 to 4095 sets of symbols from the symbol buffer. One set of symbols is
defined as either two copies of the contents of the buffer or the modified delayed
symbol set.
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Intel^® 5000X Chipset Memory Controller Hub (MCH) Datasheet