QG5000XSL9TH Datasheet, PDF (5/458 Pages) Intel Corporation – Intel 5000X Chipset Memory Controller Hub (MCH)

3.11
3.10.19PEXDEVSTS - PCI Express Device Status Register ..................................... 266
PCI Express Intel IBIST Registers ...................................................................... 267
3.11.1 DIOIBSTR: PCI Express Intel IBIST Global Start/Status Register................. 267
3.11.2 DIO0IBSTAT: PCI Express Intel IBIST Completion Status Register............... 268
3.11.3 DIO0IBERR: PCI Express Intel IBIST Error Register................................... 268
3.11.4 PEX[7:2,0]IBCTL: PEX Intel IBIST Control Register ................................... 269
3.11.5 PEX[7:2,0]IBSYMBUF: PEX Intel IBIST Symbol Buffer ............................... 270
3.11.6 PEX[7:2,0]IBEXTCTL: PEX Intel IBIST Extended Control Register ................ 271
3.11.7 PEX[7:2,0]IBDLYSYM: PEX Intel IBIST Delay Symbol ................................ 273
3.11.8 PEX[7:2,0]IBLOOPCNT: PEX Intel IBIST Loop Counter ............................... 273
3.11.9 PEX[7:2,0]IBLNS[3:0]: PEX Intel IBIST Lane Status ................................. 274
3.11.10DIO[1:0]SQUELCH_CNT: PCIe Cluster Squelch Count................................ 275
4 System Address Map ............................................................................................. 277
4.1 System Memory Address Ranges ....................................................................... 278
4.1.1 32/64-bit addressing ............................................................................ 278
4.2 Compatibility Area ........................................................................................... 280
4.2.1 MS-DOS Area (0 0000h–9 FFFFh) ........................................................... 280
4.2.2 Legacy VGA Ranges (A 0000h–B FFFFh) .................................................. 281
4.2.3 Expansion Card BIOS Area (C 0000h–D FFFFh)......................................... 282
4.2.4 Lower System BIOS Area (E 0000h–E FFFFh) ........................................... 282
4.2.5 Upper System BIOS Area (F 0000h–F FFFFh) ........................................... 283
4.3 System Memory Area....................................................................................... 283
4.3.1 System Memory ................................................................................... 283
4.3.2 15 MB - 16 MB Window (ISA Hole).......................................................... 283
4.3.3 Extended SMRAM Space (TSEG) ............................................................. 283
4.3.4 Memory Mapped Configuration (MMCFG) Region ....................................... 284
4.3.5 Low Memory Mapped I/O (MMIO) ........................................................... 285
4.3.6 Chipset Specific Range .......................................................................... 286
4.3.7 Interrupt/SMM Region........................................................................... 286
4.3.8 High Extended Memory ......................................................................... 288
4.3.9 Main Memory Region ............................................................................ 289
4.4 Memory Address Disposition ............................................................................. 289
4.4.1 Registers Used for Address Routing......................................................... 289
4.4.2 Address Disposition for Processor ........................................................... 290
4.4.3 Inbound Transactions ........................................................................... 293
4.5 I/O Address Map ............................................................................................. 295
4.5.1 Special I/O Addresses ........................................................................... 295
4.5.2 Outbound I/O Access ............................................................................ 295
4.6 Configuration Space ........................................................................................ 297
4.7 I/O Address Map ............................................................................................. 297
4.7.1 Special I/O Addresses ........................................................................... 297
4.7.2 Outbound I/O Access ............................................................................ 298
4.8 Configuration Space ........................................................................................ 298
5 Functional Description ........................................................................................... 299
5.1 Processor Front Side Buses ............................................................................... 299
5.1.1 FSB Overview ...................................................................................... 299
5.1.2 FSB Dynamic Bus Inversion ................................................................... 300
5.1.3 FSB Interrupt Overview......................................................................... 300
5.2 Snoop Filter.................................................................................................... 301
5.2.1 Snoop Filter Address Bit Mapping............................................................ 304
5.2.2 Operations and Interfaces ..................................................................... 304
5.3 System Memory Controller ............................................................................... 305
5.3.1 Memory Population Rules ...................................................................... 307
5.3.2 Fully Buffered DIMM Technology and Organization .................................... 310
5.3.3 FB-DIMM Memory Operating Modes ........................................................ 312
Intel® 5000X Chipset Memory Controller Hub (MCH) Datasheet
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