D12320VF25IV Datasheet, PDF (965/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Oscillator
Section 21 Power-Down Modes
RES
STBY
Oscillation
stabilization
time
Figure 21.3 Hardware Standby Mode Timing
Reset
exception
handling
21.8 φ Clock Output Disabling Function
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 21.5 shows the state of the φ pin in each processing state.
Table 21.5 φ Pin State in Each Processing State
DDR
PSTOP
Hardware standby mode
Software standby mode
Sleep mode
Normal operating state
0
—
High impedance
High impedance
High impedance
High impedance
1
0
Fixed high
φ output
φ output
1
Fixed high
Fixed high
Rev.6.00 Sep. 27, 2007 Page 933 of 1268
REJ09B0220-0600