D12320VF25IV Datasheet, PDF (234/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
φ
Full access
T₁
T₂
Burst access
T₁
T₁
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data Read data Read data
Figure 6.30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait
Control.
Wait states cannot be inserted in a burst cycle.
Rev.6.00 Sep. 27, 2007 Page 202 of 1268
REJ09B0220-0600