D12320VF25IV Datasheet, PDF (316/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 7 DMA Controller (Not Supported in the H8S/2321)
Full Address Mode (Cycle Steal Mode): Figure 7.20 shows a transfer example in which TEND
output is enabled and word-size full address mode transfer (cycle steal mode) is performed from
external 16-bit, 2-state access space to external 16-bit, 2-state access space.
φ
Address bus
RD
HWR
LWR
TEND
DMA
read
DMA
write
DMA
read
DMA
write
DMA
read
DMA DMA
write dead
Bus release
Bus release
Bus release Last transfer
cycle
Bus
release
Figure 7.20 Example of Full Address Mode (Cycle Steal) Transfer
A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the
bus is released one bus cycle is executed by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead
cycle is inserted after the DMA write cycle.
Rev.6.00 Sep. 27, 2007 Page 284 of 1268
REJ09B0220-0600