D12320VF25IV Datasheet, PDF (747/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 16 A/D Converter (8 Analog Input Channel Version)
16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time t_D after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D
conversion timing. Table 16.4 indicates the A/D conversion time.
As indicated in figure 16.5, the A/D conversion time includes t_D and the input sampling time. The
length of t_D varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 16.4.
In scan mode, the values given in table 16.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is as shown in table 16.5.
(1)
φ
Address bus
(2)
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Legend:
(1): ADCSR write cycle
(2): ADCSR address
t_D: A/D conversion start delay
t_SPL: Input sampling time
t_CONV: A/D conversion time
Figure 16.5 A/D Conversion Timing
Rev.6.00 Sep. 27, 2007 Page 715 of 1268
REJ09B0220-0600