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D12320VF25IV Datasheet, PDF (956/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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Section 21 Power-Down Modes
⢠The division ratio can be changed while the chip is operating. The clock output from the Ï pin
will also change when the division ratio is changed. The frequency of the clock output from
the Ï pin in this case will be as follows:
Ï = EXTAL Ã n
Where: EXTAL: Crystal resonator or external clock frequency
n:
Division ratio (n = Ï/2, Ï/4, or Ï/8)
⢠Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits
SCK2 to SCK0.
Bit 5
DIV
0
1
Description
When bits SCK2 to SCK0 are set to other than high-speed mode, medium-speed
mode is set
(Initial value)
When bits SCK2 to SCK0 are set to other than high-speed mode, a divided clock is
supplied to the entire chip
Bits 4 and 3âReserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0âSystem Clock Select 2 to 0 (SCK2 to SCK0): When the DIV bit is cleared to 0,
these bits select the bus master clock; when the DIV bit is set to 1, they select the division ratio of
the clock supplied to the entire chip.
Bit 2
SCK2
0
1
Bit 1
SCK1
0
1
0
1
Bit 0
SCK0
0
1
0
1
0
1
â
Description
DIV = 0
DIV = 1
Bus master is in high-speed
Bus master is in high-speed
mode
(Initial value) mode
(Initial value)
Medium-speed clock is Ï/2
Clock supplied to entire chip is Ï/2
Medium-speed clock is Ï/4
Clock supplied to entire chip is Ï/4
Medium-speed clock is Ï/8
Clock supplied to entire chip is Ï/8
Medium-speed clock is Ï/16
â
Medium-speed clock is Ï/32
â
â
â
Rev.6.00 Sep. 27, 2007 Page 924 of 1268
REJ09B0220-0600
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