D12320VF25IV Datasheet, PDF (17/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.5.7 Precharge State Control ....................................................................................... 187
6.5.8 Wait Control ........................................................................................................ 188
6.5.9 Byte Access Control ............................................................................................ 190
6.5.10 Burst Operation.................................................................................................... 192
6.5.11 Refresh Control.................................................................................................... 195
6.6 DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) ... 198
6.6.1 When DDS = 1..................................................................................................... 198
6.6.2 When DDS = 0..................................................................................................... 199
6.7 Burst ROM Interface......................................................................................................... 200
6.7.1 Overview.............................................................................................................. 200
6.7.2 Basic Timing........................................................................................................ 200
6.7.3 Wait Control ........................................................................................................ 202
6.8 Idle Cycle .......................................................................................................................... 203
6.8.1 Operation ............................................................................................................. 203
6.8.2 Pin States in Idle Cycle ........................................................................................ 208
6.9 Write Data Buffer Function .............................................................................................. 209
6.10 Bus Release....................................................................................................................... 210
6.10.1 Overview.............................................................................................................. 210
6.10.2 Operation ............................................................................................................. 210
6.10.3 Pin States in External Bus Released State............................................................ 211
6.10.4 Transition Timing ................................................................................................ 212
6.10.5 Usage Note........................................................................................................... 213
6.11 Bus Arbitration.................................................................................................................. 213
6.11.1 Overview.............................................................................................................. 213
6.11.2 Operation ............................................................................................................. 213
6.11.3 Bus Transfer Timing ............................................................................................ 214
6.11.4 External Bus Release Usage Note........................................................................ 215
6.12 Resets and the Bus Controller ........................................................................................... 215
Section 7 DMA Controller (Not Supported in the H8S/2321) ..........................217
7.1 Overview........................................................................................................................... 217
7.1.1 Features................................................................................................................ 217
7.1.2 Block Diagram ..................................................................................................... 218
7.1.3 Overview of Functions......................................................................................... 219
7.1.4 Pin Configuration................................................................................................. 221
7.1.5 Register Configuration......................................................................................... 222
7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 223
7.2.1 Memory Address Registers (MAR) ..................................................................... 224
7.2.2 I/O Address Register (IOAR) .............................................................................. 225
7.2.3 Execute Transfer Count Register (ETCR) ........................................................... 225
Rev.6.00 Sep. 27, 2007 Page xv of xxx
REJ09B0220-0600