D12320VF25IV Datasheet, PDF (644/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 14 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
0
Description
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
(Initial value)
• When the DMAC^* or DTC is activated by an RXI interrupt and reads data from
RDR
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Notes: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
* The DMAC is not supported in the H8S/2321.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
(Initial value)^*1
When 0 is written to ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1^*2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Rev.6.00 Sep. 27, 2007 Page 612 of 1268
REJ09B0220-0600