D12320VF25IV Datasheet, PDF (218/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5.6 Basic Timing
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4
states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or
disabling of wait insertion, and do not affect the number of access states. When the corresponding
bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
The 4 states of the basic timing consist of one T_p (precharge cycle) state, one T_r (row address
output cycle), and two T_c (column address output cycle) states, T_c1 and T_c2.
T_p
T_r
T_c1
T_c2
φ
A₂₃ to A₀
Row
Column
CSn (RAS)
CAS, LCAS
Read
HWR (WE)
D₁₅ to D₀
Write
HWR (WE)
D₁₅ to D₀
Note: n = 2 to 5
Figure 6.15 Basic Access Timing
Rev.6.00 Sep. 27, 2007 Page 186 of 1268
REJ09B0220-0600