D12320VF25IV Datasheet, PDF (915/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 19 ROM
Start
*1
Set SWE1 (2) bit in FLMCR1 (2)
Wait (x) μs
*2
n=1
Set EBR1, EBR2
*4
Enable WDT
Set ESU1 (2) bit in FLMCR1 (2)
Wait (y) μs
Set E1 (2) bit in FLMCR1 (2)
Wait (z) ms
Clear E1 (2) bit in FLMCR1(2)
Wait (α) μs
Clear ESU1 (2) bit in FLMCR1 (2)
Wait (β) μs
Disable WDT
Set EV1 (2) bit in FLMCR1 (2)
Wait (γ) μs
*2
Start of erase
*2
Halt erase
*2
*2
*2
Set block start address to verify address
n←n+1
H'FF dummy write to verify address
Wait (ε) μs
*2
Increment
address
NG
Read verify data
*3
NG
Verify data = all 1?
OK
Last address of block?
OK
Clear EV1 (2) bit in FLMCR1 (2)
Clear EV1 (2) bit in FLMCR1 (2)
Wait (η) μs
*2
NG
*5
End of
erasing of all erase
blocks?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
Wait (η) μs
*2
*2
NG
n ≥ N?
OK
Clear SWE1 (2) bit in FLMCR1 (2)
Wait (θ) μs
Wait (θ) μs
End of erasing
Erase failure
Notes: 1. Prewriting (setting erase block data to all 0) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in the section 22.2.6, Flash Memory Characteristics.
3. Verify data is read in 16-bit (W) units.
4. Set only one bit in EBR1or EBR2. More than one bit cannot be set.
5. Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 19.72 Erase/Erase-Verify Flowchart
Rev.6.00 Sep. 27, 2007 Page 883 of 1268
REJ09B0220-0600