D12320VF25IV Datasheet, PDF (344/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 Data Transfer Controller
8.1.2 Block Diagram
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register
information.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller DTC
Internal address bus
On-chip
RAM
Interrupt
request
CPU interrupt
request
Internal data bus
Legend:
MRA, MRB
: DTC mode registers A and B
CRA, CRB
: DTC transfer count registers A and B
SAR
: DTC source address register
DAR
: DTC destination address register
DTCERA to DTCERF : DTC enable registers A to F
DTVECR
: DTC vector register
Figure 8.1 Block Diagram of DTC
Rev.6.00 Sep. 27, 2007 Page 312 of 1268
REJ09B0220-0600