D12320VF25IV Datasheet, PDF (491/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 10 16-Bit Timer Pulse Unit (TPU)
Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
0
0000
TGR0D Output disabled
(Initial value)
1
1
0
is output _{Initial output is 0 0 output at compare match}
compare
register*²
output
1 output at compare match
1
Toggle output at compare
match
1
0
0
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1000
1
1*
TGR0D Capture input
is input source is
capture TIOCD0 pin
register^*2
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
1
*
*
Capture input Input capture at TCNT1
source is channel count-up/count-down^*1
1/count clock
*: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and φ/1 is used as the TCNT1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev.6.00 Sep. 27, 2007 Page 459 of 1268
REJ09B0220-0600