D12320VF25IV Datasheet, PDF (137/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Exception Handling
Internal Prefetch of first
Vector fetch _{processing program instruction}
φ
RES
*
*
*
Address bus
RD
HWR, LWR
D₁₅ to D₀
(1)
(3)
High
(2)
(4)
(5)
(6)
(1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002)
(2), (4) Start address (contents of reset exception vector address)
(5) Start address ((5) = (2), (4))
(6) First program instruction
Note: * 3 program wait states are inserted.
Figure 4.2 Reset Sequence (Mode 4)
4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx:32, SP).
4.2.4 State of On-Chip Supporting Modules after Reset Release
After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC* and
DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read
or written to. Register reading and writing is enabled when module stop mode is exited.
Note: * The DMAC is not supported in the H8S/2321.
Rev.6.00 Sep. 27, 2007 Page 105 of 1268
REJ09B0220-0600