D12320VF25IV Datasheet, PDF (205/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed, the upper half (D₁₅ to D₈) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T₁
T₂
φ
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
High
Valid
High impedance
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space
Rev.6.00 Sep. 27, 2007 Page 173 of 1268
REJ09B0220-0600