D12320VF25IV Datasheet, PDF (375/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 8 Data Transfer Controller
Input circuit
First data
transfer register
information
Second data
transfer register
information
Chain transfer
(counter = 0)
Input buffer
Upper 8 bits
of DAR
Figure 8.13 Chain Transfer when Counter = 0
Software Activation: An example is shown in which the DTC is used to transfer a block of 128
bytes of data by means of software activation. The transfer source address is H'1000 and the
destination address is H'2000. The vector number is H'60, so the vector address is H'04C0.
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
[2] Set the start address of the register information at the DTC vector address (H'04C0).
[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
Rev.6.00 Sep. 27, 2007 Page 343 of 1268
REJ09B0220-0600