D12320VF25IV Datasheet, PDF (219/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 6 Bus Controller
6.5.7 Precharge State Control
When DRAM is accessed, an RAS precharging time must be secured. With the chip, one T_p state
is always inserted when DRAM space is accessed. This can be changed to two T_p states by setting
the TPC bit in MCR to 1. Set the appropriate number of T_p cycles according to the DRAM
connected and the operating frequency of the chip. Figure 6.16 shows the timing when two T_p
states are inserted.
When the TCP bit is set to 1, two T_p states are also used for refresh cycles.
T_p1
T_p2
T_r
T_c1
T_c2
φ
A₂₃ to A₀
Row
Column
CSn (RAS)
CAS, LCAS
HWR (WE)
Read
D₁₅ to D₀
Write
HWR (WE)
D₁₅ to D₀
Note: n = 2 to 5
Figure 6.16 Timing with 2-State Precharge Cycle
Rev.6.00 Sep. 27, 2007 Page 187 of 1268
REJ09B0220-0600