D12320VF25IV Datasheet, PDF (608/1304 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 12 8-Bit Timers
12.6.3 Contention between TCOR Write and Compare Match
During the T₂ state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs.
Figure 12.12 shows this operation.
TCOR write cycle by CPU
T₁
T₂
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare match signal
TCOR write data
Prohibited
Figure 12.12 Contention between TCOR Write and Compare Match
Rev.6.00 Sep. 27, 2007 Page 576 of 1268
REJ09B0220-0600